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SX1223
The single sided frequency deviation ? f is half of the difference between f 0 and f 1 . Bit rates from 1.2 to 19.2 kbit/s
are achievable with this method.
4.3 POWER AMPLIFIER
The output power of the PA is programmable in 8 steps, with approximately 3 dB between each step. This is
controlled by bits PA2 to PA0 according to Table 6 below. PA2..PA0 = 111 provides the maximum output power of
typically 10 dBm.
PA2
0
0
0
0
1
1
1
1
PA1
0
0
1
1
0
0
1
1
PA0
0
1
0
1
0
1
0
1
Output power
21dB attenuation
18dB attenuation
15dB attenuation
12dB attenuation
9dB attenuation
6dB attenuation
3dB attenuation
Maximum power
Table 6 : PA power settings
The PA is normally controlled by the two Mode bits (off for all cases other than Mode1, Mode0 = ‘11’). The PA can
in addition be controlled by the lock detector, if the bit PALDc_en is set high (and LD_en=’1’). In this case, once LD
goes high after entering the transmit mode, the PA is turned on and will remain on until a new event changing the
working mode occurs (such as a new configuration transmitted through the 3-wire interface).
During open loop VCO modulation, mw2, the PLL is deactivated during the transmission time. After an open loop
transmission, the frequency may have drifted off, and it is therefore important that the PA is turned off before the
PLL is activated. The PA behaves this way as long as PALDc_en=1. After a transmission burst, DATAIN must be
set to high impedance, the PA is turned off and the PLL is reactivated. Once LD goes high again, the PA is turned
on and a new burst of data can be transmitted.
To reduce the harmonics for passing the ETSI and FCC regulations a 3 rd order LC-filter (T or Π configuration)
should be implemented between the output of the PA and the antenna port.
The ramp-up of the PA is achieved using an internal capacitor (approx. 29pF). If this is not sufficient to pass
relevant regulations, bit PAC_en can be enabled and an external capacitor connected to pin 6.
Using PA_IB3,2 and PAB_IB3,2 bits the reference current can be selected to bias the PA and the PA buffer as
shown in Table 31.
An 82k
resistor should be connected between pin 24 and ground for the CI bias. If the option PTAT bias source
with external resistor is chosen, an 18k
resistor should be connected between pin 6 and ground.
This option can not be used when PAC_en option is selected. In this case the resistor is replaced by a capacitor,
and the functionality changes as described above.
4.4 VOLTAGE REGULATORS
The SX1223 has three internal Low Dropout Regulators (LDOs) powering up different parts of the circuit, as can be
seen from the block diagram (Figure 1). The LDOs can be turned off (default setting is on) by setting the
LDO_en=’0’.
When LDO_en=’1’, the power supply range is 2.2 - 3.6 V (sv1). Power must be applied to pins 1 and 11. A good
quality factor capacitor is needed on each of the LDO output for stability (pins 3, 9 and 23). In sleep mode all the
LDOs are turned off. The interface and control blocks run on unregulated power, and the register contents will be
stored and hence the device can be programmed whilst in this mode.
When LDO_en=0, the power supply range is 2.0 - 2.5 V (sv2). Power must be applied to pin 1, 3, 9, 11 and 23. In
this case capacitors are only needed for normal noise decoupling.
? Semtech 2007
14
www.semtech.com
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